The present application relates to semiconductor manufacturing, and more particularly to a method and structure to enable improved dielectric spacer reactive ion etch (RIE) endpoint detection.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
In the fabrication of FinFET devices, a controlled dielectric spacer pull down process is critical to enable source/drain epitaxy growth and prevent the formation of an epitaxial semiconductor nodule. Utilizing current technology, the control of a spacer pull down process is challenging because there is no reliable endpoint signal to detect. Moreover, the current processes for the removal of a dielectric spacer that is present on top of an insulator layer as well as on the sidewall surfaces of a semiconductor fin that extend upwards from the insulator layer do not provide enough of an endpoint detection signal change for reliable endpoint detection.
As such, there is a need for providing a method and structure to enable dielectric spacer endpoint detection that overcomes the problems associated with prior art processes of removing dielectric spacers during fabrication of finFET devices.